1. Field of the Invention
This invention relates to EPROM memory devices and more particularly to enhancement mode EPROM and flash EEPROM devices and method of fabrication of such devices.
2. Description of Related Art
EPROM (Erasable Programmable Read Only Memory) FET semiconductor devices provide long term retention of charge to store data. The charge is stored on a floating gate electrode which is not electrically connected to a terminal. Instead, the charge is supplied to the floating gate electrode through an insulator. The data may be erased by exposure of the device to ultraviolet light to erase the stored data by discharging the floating gate electrode.
EEPROM (Electrically Erasable Programmable Read Only Memory) FET semiconductor devices can be erased by electrical means instead of exposure to ultraviolet light.
Flash EPROM devices are EEPROM FET devices with a double gate electrode structure including a floating gate electrode and a control gate electrode with a dielectric layer thickness of about 100 xc3x85 thickness.
U.S. Pat. No. 5,198,380 (Harari); U.S. Pat. No. 4,816,883 (Baldi); U.S. Pat. No. 4,646,425 (Owens et al.) show methods of forming EPROM devices. However, these differ from the EEPROM of the invention.
U.S. Pat. No. 5,506,816 (Hirose et al.) shows a memory cell array having a compact word line arrangement. A subword line drives circuit has an NMOS transistor and a PMOS transistor, with the drain of the NMOS transistor and the source of the NMOS transistor connected to the word line. The source of the NMOS transistor and the drain of the PMOS transistor are connected to the receive a word line selection signal from a common source line. However, this differs form the EEPROM of the invention.
U.S. Pat. No. 5,506,803 (Jex) shows a memory device where the driver is a P-channel MOS having an N-well which is used program. However this differs from the EEPROM of the invention which uses a P-channel MOS to program and a N-channel MOS to write.
Problems which can occur with P-channel EEPROM devices include the fact that a P-channel EEPROM has higher Channel Hot Electron (CHE) injection current at lower gate voltage, and a P-channel EEPROM has serious drain disturbance and depletion issues.
Objects of this invention are to provide larger programming current and lower power dissipation; no drain disturbance; and enhancement mode devices instead of depletion mode devices.
Features of this invention are as follows:
1. An EEPROM device in accordance with this invention is programmed by the P-channel MOSFET and is read by an N-channel MOSFET which is integral with the P-channel with a shared floating gate and a shared control gate.
2. Thus the P-channel portion of the EEPROM is employed as a programming current injector.
3. The Read is provided by the N-channel portion of the EEPROM (or Flash EPROM).
4. One P-channel portion of an omnibus EEPROM can make contact to 1, 2, 4 or more N-channel portions of an EEPROM.
A method of forming an FET semiconductor device in accordance with this invention starts with a doped silicon semiconductor substrate having a surface, the substrate being lightly doped with a first type of dopant includes the following steps.
Form an N-region and a P-region in the substrate with the N-region in side by side relationship with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. Form the following gate electrode layers into a gate electrode stack by the following steps.
a) Form a tunnel oxide layer over the surface of the substrate above the N-region and the P-region covering the first channel and the second channel, the P+ drain region, the N+ drain region and the interface,
b) Form a floating gate electrode layer over the tunnel oxide layer,
c) Form an interelectrode dielectric layer over the floating gate electrode,
d) Form a control gate electrode layer over the interelectrode dielectric layer,
e) Pattern the gate electrode layers comprising the tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode into a gate electrode stack with a mask spanning across the N-region and the P-region.
f) Etch away exposed portions of the gate electrode layers to provide a gate electrode stack spanning across the N-region and the P-region.
Then form N+ source/drain regions for an N-channel device in the P-region self-aligned with the stack; and form P+ source/drain regions for an N-channel device in the N-region self-aligned with the stack.
Then ion implant an N+ drain region in the surface of the P-region with an N type of dopant, the N+ drain region being self-aligned with the gate electrode stack, and ion implant a P+ drain region in the surface of the N-region with an N type of dopant. The P+ drain region is self-aligned with the gate electrode stack.
The P+ source/drain dopant comprises P type dopant ions of boron fluoride ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 14 ions/cm2 to about 1 E 15 ions/cm2.
The N+ source/drain dopant comprises N type dopant ions of arsenic ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 14 ions/cm2 to about 1 E 15 ions/cm2.
The tunnel oxide layer is from about 80 xc3x85 to about 100 xc3x85 thick.
The floating gate electrode comprises a layer from about 1,000 xc3x85 about 1,200 xc3x85 thick.
The interelectrode layer comprises a dielectric layer from about 150 xc3x85 to about 300 xc3x85 thick.
The control gate electrode comprises a layer from about 1,500 xc3x85 to about 3,000 xc3x85 thick.
The P-substrate is doped by P type dopant comprising boron atoms with a concentration from about 1 E 13 atoms/cm3 to about 1 E 15 atoms/cm3.
Also in accordance with this invention, an FET semiconductor device is formed on a doped silicon semiconductor substrate having a surface, the substrate being lightly doped with a first type of dopant includes an N-region and a P-region formed in the substrate with the N-region side by side relationship with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. A gate electrode stack over the surface of the substrate above the first channel and the second channel with the gate electrode stack bridging the channels in the N-region and the P-region. The source and drain N+ doped regions formed on opposite sides of the first channel in the P-region self-aligned with the gate electrode stack. The source and drain P+ doped regions formed on opposite sides of the first channel in the N-region self-aligned with the gate electrode stack.
The gate electrode stack extends as a common gate electrode stack from a single FET in a first one of the N-region and the P-region in the substrate to a plurality of FET devices in the other one of the N-region and the P-region.
The gate electrode stack extends as a common gate electrode stack from a single FET in a first one of the N-region and the P-region in the substrate to a plurality of FET devices arranged in series along the control gate electrode in the other one of the N-region and the P-region.
Alternatively, the gate electrode stack extends as a common gate electrode stack from a single FET in a first one of the N-region and the P-region in the substrate to a plurality of FET devices arranged in parallel along the control gate electrode in the other one of the N-region and the P-region.
The stack includes a tunnel oxide layer from about 80 xc3x85 to about 100 xc3x85 thick and a floating gate electrode comprising a layer from about 1,000 xc3x85 to about 1,200 xc3x85 thick.
The floating gate electrode is formed an interelectrode layer comprising a dielectric layer from about 150 xc3x85 to about 300 xc3x85 thick.
The interelectrode layer is formed a control gate electrode having a thickness from about 1,500 xc3x85 to about 3,000 xc3x85.
The P+ source/drain dopant comprises P type dopant atoms with a concentration from about 1 E 18 atoms/cm3 to about 1 E 20 atoms/cm3, and the N+ source/drain dopant comprises N type dopant atoms with a concentration from about 1 E 18 atoms/cm3 to about 1 E 20 atoms/cm3.
The P-substrate is doped by P type dopant boron atoms with a concentration from about 1 E 13 atoms/cm3 to about 1 E 15 atoms/cm3, the tunnel oxide layer is from about 80 xc3x85 to about 100 xc3x85 thick, the floating gate electrode comprises a layer from about 1,000 xc3x85 to about 1,200 xc3x85 thick, the interelectrode layer comprises a dielectric layer from about 150 xc3x85 to about 300 xc3x85 thick, the control gate electrode comprises a layer from about 1,500 xc3x85 to about 3,000 xc3x85 thick. The P+ source/drain dopant comprises P type dopant atoms of boron fluoride with a concentration from about 1 E 18 atoms/cm3 to about 1 E 20 atoms/cm3, and the N+ source/drain dopant comprises N type dopant atoms of arsenic with a concentration from about 1 E 18 atoms/cm3 to about 1 E 20 atoms/cm3.